The following references provide useful background information on the indicated topics, all of which relate to the invention, and are incorporated herein by reference.
Low power techniques based upon glitch reduction for register-transfer level circuits:
    A. Raghunathan, S. Dey and N. K. Jha, Glitch Analysis And Reduction In Register-Transfer-Level Power Optimizatlon, IEEE Proc. of Design Automation Conference (DAC96), pp. 331-336 (1996).Synthesis environment using high-level power estimation:    A. Chandrakasan, M. Potkonjak, 3. Rabaey and R. Brodersen, Hyper-LP: A System for Power Minimization using Architectural Transformations, IEEE Proc. of Int'l Conf. on Computer-Aided Design (IC-CAD92), pp. 300-303 (1992).Optimization of power consumption with high level design methodologies:    G. Lakshminarayana, A. Raghunathan, K. S. Khourl and N. K. Jha, Common Case Computation: .A High-Level Power-Optimizing Technique, IEEE Proc. of Design Automation Conference (DAC99), pp. 1-6 (June 1999).Use of object-oriented techniques to improve the hardware design process:    S. Kumar, 1. Aylor, B. Johnson and W. Wuif, Object-Oriented Techniques in Hardware Design, IEEE Computer, Vol. 27, pp. 64-70 (June 1994).Simulation environment to evaluate the number of cycles for application processing:    F. Mallet, F. Hoed, and J. F. Duboc, Hardware Architecture Modeling Using an Object-Oriented Method, Proceedings of the 24th EUROMICRO Conference, pp. 147-153 (August 1998).Using JAVA for concurrent modules and asynchronous communication therebetween:    C. Passerone, R. Passerone, C. Sansoe, J. Martin, A. Sangiovanni-Vincentelli and R. McGeer, Modeling Reactive Systems in Java, Proceedings of the Sixth International Workshop on Hardware/Software Codesign, pp. 15-19 (March 1998).Techniques for system specification refinement:    J. S. Young, J. MacDonald, M. Shilman, A. Tabbara, P. Hillfinger and A. R. Newton, Design and Specification of Embedded Systems in Java using Successive Format Refinement, Proceedings of the Design and Automation Conference, pp. 70-75 (June 1998).Design and incorporation of core models into system-level specifications:    F. Vahid and T. Givargis, Incorporating Cores into System-Level Specification, International Symposium on System Synthesis, pp. 43-48 (December 1998).Bus configurations for a given set of communications channels:    T. Givargis and F. Vahid, Interface Exploration for Reduced Power in Core-Based Systems, International Symposium on System Synthesis, pp. 117-122 (December 1998).Core-based modeling for systems-on-a-chip:    T. Givargis, 1. Henkel and F. Vahid, Interface and Cache Power Exploration for Core-Based Embedded System Design, Submitted to International Conference on Computer Aided Design (November 1999).Modeling switching activity for on-chip and off-chip busses;    W. Fornaciari, D. Sciuto and C. Silvano, Power Estimation for Architectural Explorations of HW/SW Communication on System-Level Buses, To be published at HW/SW Codesign Workshop, Rome, pp. 152-156 (May 1999).Empirical model for multi-level interconnect capacitance:    Jue-Hsien Chem, Jean Huang, Lawrence Arledge, Ping-Chung Li and Ping Yang, Multilevel Metal Capacitance Models for CAD Design Synthesis Systems, IEEE electron Device Letters, Vol. 13, No. 1, pp. 32-34 (January 1992).Background and future trends in rapid silicon prototyping:    B. Payne, Rapid Silicon Prototyping: Paradigm for Custom System-on-a-Chip Design, http://www.vlsi.com/velocity (1998).Functional verification of large ASICs:    A. Evans, A. Silburt G. Vrckovnik, T. Brown, M. Dufresne, G. Hall, T. Ho and Y. Liu, Functional Verification of Large ASICs, Design Automation Conference, pp. 650-665 (1998).Fundamentals of core-based design:    R. Gupta and Y. Zorian, Introducing Core-Based System Design, IEEE Design and Test, Vol. 14, No. 4, pp. 15-25 (Oct.-Dec. 1997).    There will now be provided a discussion of various topics to provide a proper foundation for understanding the invention.
As chip capacities continue to grow, enabling systems-on-a-chip (hereinafter “SOC”), the need for early simulation of system-level models increases. A system-level model describes desired behavior without describing detailed structural or timing information, and such models are often specified in executable languages like C++ or JAVA, eliminating the need for a separate simulation tool. Such models thus simulate many orders of magnitude faster than lower-level models like register-transfer or gate-level hardware description language (hereinafter “HDL”) models, turning otherwise week-long or month-long simulations into just minutes or hours. These models are useful for early observation of system behavior and perhaps high-level performance information and thus designers taking a top-down approach often build and simulate such models before developing lower-level models. However, system-level models have the disadvantage of not providing sufficiently accurate information on detailed design metrics like power consumption and size, so architectural design decisions must often be postponed until later in the design process when lower-levels models are available.
A core is a reusable system-level component, such as a microprocessor, coprocessor or peripheral component, designed to become part of a SOC. Usually a core is a pre-designed, pre-verified silicon circuit block containing upwards of five thousand gates that can be used in building a larger or more complex application on a semiconductor chip. A soft core consists of a synthesizeable HDL description that can be re-targeted to different semiconductor processes. A firm core contains more structure, usually a gate-level netlist that is ready for placement and routing. A hard core includes layout and technology-dependent timing information as is ready to be dropped into a system. By many estimates, SOCs will consist mostly of cores, perhaps upwards of ninety percent, with custom synthesized logic comprising the small remaining portion. Because cores are often parameterized and their interconnecting bus structure may be flexible, core-based designs still involve a large design space and hence many architectural design decisions.
The Virtual Socket Interface Alliance (hereinafter “VSIA”) is an industry consortium developing core-related standards. Those standards include the development of system-level models for all cores (whether soft, firm or hard). The situation of system-level models representing already-designed components provides a unique opportunity. In particular, it would be particularly useful for the developer of a core's system-level model to have information on the core's power, performance and size metrics (unlike the case when the model was created by a designer following the top-down approach), since a low-level model does exist for cores. Since the core developer wants the core to be re-used, we can: expect the developer to expend effort incorporating such metric information into the core's system-level model. This opportunity can be used to overcome the earlier-stated disadvantage of inaccurate estimates from system-level models, and thus can enable extensive design space exploration at the system level.
As for the register transfer language level (hereinafter “RTL”) approaches described in the literature, a power optimization method has been introduced that minimizes power at the architectural level (RTL-level) by using a macro model scheme. The Hyper-LP described in the literature belongs to the same group. Hyper-LP is a framework that optimizes power consumption of data-dominated systems through architectural transformations. Recently, Lakshminarayana, et al. put forth a behavioral-level power optimization method called common-case computation. So called common cases are exploited in order to synthesize a compact datapath such that power reductions of up to around ninety-two percent become possible.
As for high-level modeling, Kumar, et al. proposes modeling of hardware components, e.g., comparators and registers, as objects communicating via method calls. These objects serve as the building blocks of complex systems. Mallet, et al. proposes similar modeling of components communicating with each other via ports and signals allowing for good estimation of performance. However, modeling complex digital systems requires modeling of components at higher levels of abstraction, e.g., processors and JPEG encoders.
Other researchers have contributed object-oriented models, mainly based on JAVA, that enable hardware description at a behavioral abstraction level. In addition to providing models for capture and simulation of digital systems, these contributions provide solutions to problems —such as: ease of conversion from high-level description to hardware description for synthesis, modeling of reactive systems, and deterministic modeling of digital systems with bounded resource allocation. To the best of our knowledge, these contributions do not provide means for power and area and performance estimation at the system level.
Vahid and Givargis propose specification of more abstract components, i.e., SOC cores, that communicate via method-calling or message-passing. Their high-level model and functional communication allows for exploration of SOC busses for low power. Other work by Givargis, et al. extends this exploration with power and performance results obtained from CPU, interface and cache simulations.